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Tag Archive energy-efficiency

Tag lists for SBMeS

Adaptive,adaptive TT,Adaptivity,algorithm,Algorithm,AM,Application model,automotive,automotive functions,CM,Collision,
complex integrated systems,
computer science,
Context model,
critical events,
Decision Variables,  dependability,
Embedded Real-Time Systems,
embedded systems,
energy consumption,
energy efficiency,  energy saving,
energy-aware,  energy-efficiency,  Energy-efficiency,
execution time,
fault events,  flexibility,
frequency scaling,
Gannt mapping,
global optimum,
Graph mapping,
mathematical programming,
Message Deadlines,
Message Duration,
Mixed-Integer Quadratic Programming,
mobile phones,
Motivation, MPSoC,
multi-core architectures,
neighborhood search,
Neighborhood search,
objective function,
Physical model,
quasi-static scheduling,
Real-time Systems,
safety-critical systems,
Slow Down Factors,
Task Procrastination,
Time-Triggered Embedded Systems,  tree-based graph,
TT systems,



Event tree

List of Figures

Figure 1. Conceptual difference [23] 
Figure 2. Current and future trend in an embedded system [23] ….
Figure 3. Kalray’s MPPA network-on-chip (The MPPA2®−256 Bostan2 processor [52]) 
Figure 4. Simplified design flow and meta-scheduler (MeS) integration in SAFEPOWER [3]Figure 5. A search tree for time slot [17] 
Figure 6. Conceptual physical model (PM) 
Figure 7. General physical model (PM) schema 
Figure 8. General application model (AM) schema 
Figure 9. General context model (CM) schema 
Figure 10. Meta-scheduler (MeS) data structure schema model 
Figure 11. The basic model of meta-scheduling (MeS) 
Figure 12. Conceptual AM
Figure 13. Quadratization technique via hops .
Figure 14.The effect of TSDF on tasks et(t) and core fault 
Figure 15. Three-step scheduling for finding optimum solutions 
Figure 16. a. Stack slack (SS) and b. Dynamic slack (DS) sample 1
Figure 17. Usage of dynamic slack (DS) to reduce makespan

Figure 18. Usage of SDF regarding dynamic slack (DS) 
Figure 19. Usage of scenario-based meta-scheduling (SBMeS) on system-level design for SAFEPOWER multi-processor system-on-a-chip (MPSoC) [3] 
Figure 20. Depth-first algorithm establishing schedule backwards with tabu-set for re-convergence (FAESB-TSR) 
Figure 21. Conceptual of the meta-scheduler (MeS) tool 
Figure 22. Scenario-based meta-scheduling (SBMeS) general model 
Figure 23. States of 3 events and their effect of each SM 
Figure 24. Events’ effects in task scheduling 
Figure 25. Schedule Gantt map 
Figure 26. Schedule tree include all data 
Figure 27. Meta-visualization of an event 
Figure 28. Events state in s schedule tree 
Figure 29. Schedules share points regarding task changes and Figure 28 
Figure 30. Decoding schedules from delta tree (DT) 
Figure 31. Delta tree (DT) data model 
Figure 32. Schema technique for standard data structure modelling 
Figure 33. Overview of scheduling models 
Figure 34. The simple architecture of meta-scheduling (MeS) 
Figure 35. Standardized input XML sample 
Figure 36. Example a textual data with three nodes 
Figure 37. Static slack (SS) schedule model (SM) generated by meta-scheduling visualization tool (MeSViz) 
Figure 38. Schedule tree with 94 schedules (created via meta-scheduling visualization tool (MeSViz) and GVEdit) 
Figure 39. Gantt map of schedule ID 44 
Figure 40. Incorrect results and information found in the complex schedule 
Figure 41. Meta-schedule Gantt map generated from meta-scheduling (MeS) class
Figure 42. Schedule SM0 with static slack (SS) 
Figure 43. Schedule SM1 with dynamic slack (DS) 
Figure 44. Comparing two schedules SM0 (Figure 42) and SM1 (Figure 43) after slack 
Figure 45. Graph output of node dependency 
Figure 46. Few changes from ID2 to ID3
Figure 47. Minimum changes from SM37 to SM38 regarding T3 slack 
Figure 48. Meta-visualization for Example 3 (schedules SM3 & SM4) 
Figure 49. Comparison of three different scenarios for memory saving with delta scheduling technique (DTS) 
Figure 50. The physical model (PM) of case study 
Figure 51. The application model (AM) of case study 
Figure 52. The application model (AM) of the case study [6] 
Figure 53. The physical model (PM) of the case study 7.3.2 
Figure 54. Energy consumption results for cores and routers FECsm ,FERsm , FEC,avg,dyn ,FER,avg,dyn
Figure 55. FEsm schedule models( SMs) results and average FEavg,dyn 
Figure 56. Total energy reduction results for coresReFEC(SM) and routers ReFER(SM) and averageFEC,avg,dyn, FER,avg,dyn 
Figure 57.Total FE reduction results for schedules ReEsm and average ReFE 
Figure 58. The application model (AM) of the case study 
Figure 59. The physical model (PM) of the case study 
Figure 60. FECsm,FERsm results for cores and routers and average FEC,avg,dyn, FER,avg,dyn 
Figure 61. FE(sm) results and average FEavg,dyn 
Figure 62. FE results for cores ReFEC(SM) and routers ReFER(SM) compare to SM0 and average FEC,avg,dyn, FER,avg,dyn 
Figure 63. Total ReFE(sm) in each schedule compare to SM0 and average FEavg,dyn 
Figure 64. The physical model (PM) of the case study 
Figure 65. The application model (AM) of case study 
Figure 66. All nodes in a sample schedules tree 
Figure 67. Real nodes in a sample schedules tree 
Figure 68. Combination dynamic slack (DS) and core fault results in SM101 which generated by meta-scheduling visualization tool (MeSViz) 
Figure 69. The total number of generated schedules Nsm for each scenario 
Figure 70.Time of computation for scenarios 
Figure 71. FE results for each scenario SSMx 
Figure 72. Total ReFE(SMM) (percentage) results for each scenario of comparing dynamic schedules with a static schedule SMx 

Meta-schedule Gannt map

List of Tables

Table 1. An overview of related works compared to scenario-based meta-scheduling (SBMeS) 
Table 2. Overview of existing real-time scheduling tools [7] 
Table 3. Overview of input table [90] 
Table 4. Sample data calculated for Figure 14 
Table 5. Sample raw input data before forming in XML format 
Table 6. Difference between the designed scenarios 
Table 7. Results of dynamic slack (DS) schedules 
Table 8. Memory consumption and saving via delta scheduling technique (DST)
Table 9. Sample results of Example 2
Table 10. Results of delta scheduling technique (DST) memory saving for Example 2 
Table 11. Sample results for Example 3 
Table 12. Results of delta scheduling technique (DST) memory saving for Example 3 
Table 13. Meta-scheduling (MeS) input constant 
Table 14. Results of delta scheduling technique (DST) memory saving 
Table 15. Some collected results for model example 
Table 16. Energy results for example 
Table 17. Meta-scheduling (MeS) input constant devices [13] 
Table 18. Energy results for Example 7.3.2 
Table 19. General results for a model example 
Table 20. Results of delta scheduling technique (DST) memory saving 
Table 21. Meta-scheduling (MeS) input constant 
Table 22. General results of for the example model 
Table 23. Results of delta scheduling technique (DST) memory saving 
Table 24. The context model (CM) for application model (AM) and physical model (PM) scenarios 
Table 25. Meta-scheduling (MeS) input constant 
Table 26. Output results
Table 27. Redundancy path routing effect 

List of Algorithms

Algorithm 1. Main function algorithm
Algorithm 2. Fault recovery and scheduling technique
Algorithm 3. DTS discover and calculating changes for messages (a) and tasks (b) ….. 83
Algorithm 4. XML parser
Algorithm 5. Slope Evaluation 1
Algorithm 6. Slope Evaluation 2


[1] H. Kopetz, Real-time systems: design principles for distributed embedded applications: Springer Science & Business Media, 2011.
[2] J. Theis, G. Fohler, and S. Baruah, “Schedule table generation for time-triggered mixed criticality systems,” Proc. WMC, RTSS, pp. 79–84, 2013.
[3] Safepower, D3.8 User guide of the heterogeneous MPSoC design. [Online] Available: http://safepower-project.eu/wp-content/uploads/2019/01/D3.8-User_guide_of_the_heterogeneous_MPSoC_design_v1-0_final.pdf.
[4] DW BUSINESS, BMW increases R&D spending on e-cars, autonomous vehicles.
[5] S. R. Sakhare and M. S. Ali, “Genetic algorithm based adaptive scheduling algorithm for real time operating systems,” International Journal of Embedded Systems and Applications (IJESA), vol. 2, no. 3, pp. 91–97, 2012.
[6] R. Obermaisser, Ed., Time-triggered communication. Boca Raton, FL: CRC Press, 2012.
[7] P. Munk, “Visualization of scheduling in real-time embedded systems,” University of Stuttgart, Institute of Software Technology, Department of Programming Languages and Compilers, 20103.
[8] S. Hunold, R. Hoffmann, and F. Suter, “Jedule: A Tool for Visualizing Schedules of Parallel Applications,” in 2010 International Conference on Parallel Processing Workshops (ICPPW), San Diego, CA, USA, pp. 169–178.
[9] H. Wang, L.-S. Peh, and S. Malik, “Power-driven design of router microarchitectures in on-chip networks,” in 36th International symposium on microarchitecture, San Diego, CA, USA, 2003, pp. 105–116.
[10] B. Sorkhpour and R. Obermaisser, “MeSViz: Visualizing Scenario-based Meta-Schedules for Adaptive Time-Triggered Systems,” in AmE 2018-Automotive meets Electronics; 9th GMM-Symposium, 2018, pp. 1–6.
[11] A. C. Persya and T. R. G. Nair, “Model based design of super schedulers managing catastrophic scenario in hard real time systems,” in 2013 International Conference on Information Communication and Embedded Systems (ICICES), Chennai, 2013, pp. 1149–1155.
[12] B. Sorkhpour, O. Roman, and Y. Bebawy, Eds., Optimization of Frequency-Scaling in Time-Triggered Multi-Core Architectures using Scenario-Based Meta-Scheduling: VDE, 2019.
[13] B. Sorkhpour, A. Murshed, and R. Obermaisser, “Meta-scheduling techniques for energy-efficient robust and adaptive time-triggered systems,” in Knowledge-Based Engineering and Innovation (KBEI), 2017 IEEE 4th International Conference on, 2017, pp. 143–150.

[14] J. Huang, C. Buckl, A. Raabe, and A. Knoll, “Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems,” in 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, Ayia Napa, Cyprus, 2011, pp. 447–454.
[15] S. Prabhu, B. Grot, P. Gratz, and J. Hu, “Ocin tsim-DVFS aware simulator for NoCs,” Proc. SAW, vol. 1, 2010.
[16] Roman Obermaisser et al., “Adaptive Time-Triggered Multi-Core Architecture,” Designs, vol. 3, no. 1, p. 7, 2019.
[17] H. Kopetz, Ed., Real-Time Systems: Design Principles for Distributed Embedded Applications (Real-Time Systems Series) // Real-time systems: Design principles for distributed embedded applications, 2nd ed. New York: Springer, 2011.
[18] F. Guan, L. Peng, L. Perneel, H. Fayyad-Kazan, and M. Timmerman, “A Design That Incorporates Adaptive Reservation into Mixed-Criticality Systems,” Scientific Programming, vol. 2017, 2017.
[19] Y. Lin, Y.-l. Zhou, S.-t. Fan, and Y.-m. Jia, “Analysis on Time Triggered Flexible Scheduling with Safety-Critical System,” in Chinese Intelligent Systems Conference, 2017, pp. 495–504.
[20] IEEE, “TTP – A Time-Triggered Protocol For Fault-tolerant Real-time System – Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposi,”
[21] J. Cortadella, A. Kondratyev, L. Lavagno, C. Passerone, and Y. Watanabe, “Quasi-static scheduling of independent tasks for reactive systems,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 10, pp. 1492–1514, 2005.
[22] R. Rajaei, S. Hessabi, and B. V. Vahdat, “An energy-aware methodology for mapping and scheduling of concurrent applications in MPSOC architectures,” in Electrical Engineering (ICEE), 2011 19th Iranian Conference on, 2011, pp. 1–6.
[23] A. Menna, “Allocation, Assignment and Scheduling for Multi-processor System on Chip,” PhD, Universit ´e des Sciences et Technologies de Lille, 2006.
[24] A. Murshed, “Scheduling Event-Triggered and Time-Triggered Applications with Optimal Reliability and Predictability on Networked Multi-Core Chips,”
[25] A. Maleki, H. Ahmadian, and R. Obermaisser, “Fault-Tolerant and Energy-Efficient Communication in Mixed-Criticality Networks-on-Chips,” in 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, pp. 1–7.
[26] P. Eitschberger, S. Holmbacka, and J. Keller, “Trade-Off Between Performance, Fault Tolerance and Energy Consumption in Duplication-Based Taskgraph Scheduling,” in Architecture of Computing Systems – ARCS 2018.
[27] R. Lent, “Grid Scheduling with Makespan and Energy-Based Goals,” Journal of Grid Computing, vol. 13, no. 4, pp. 527–546, 2015.
[28] P. Eitschberger, “Energy-efficient and Fault-tolerant Scheduling for Manycores and Grids,” Fakultät für Mathematik und Informatik, FernUniversität in Hagen, Hagen, 2017.
[29] A. Murshed, “Scheduling event-triggered and time-triggered applications with optimal reliability and predictability on networked multi-core chips,” Dissertation, Embedded Systems, Universität Siegen, Siegen, 2018.
[30] E. Dubrova, Fault-Tolerant Design. New York, NY: Springer; Imprint, 2013.
[31] A. Avizienis, J.-C. Laprie, B. Randell, and others, Fundamental concepts of dependability: University of Newcastle upon Tyne, Computing Science, 2001.
[32] I. Bate, A. Burns, and R. I. Davis, “A Bailout Protocol for Mixed Criticality Systems,” in 2015 27th Euromicro Conference on Real-Time Systems: ECRTS 2015 : proceedings, Lund, Sweden, 2015, pp. 259–268.
[33] A. Burns and R. Davis, “Mixed criticality systems-a review,” Department of Computer Science, University of York, Tech. Rep, pp. 1–69, 2013.
[34] B. Hu et al., “FFOB: efficient online mode-switch procrastination in mixed-criticality systems,” Real-Time Syst, vol. 79, no. 1, p. 39, 2018.
[35] H. Isakovic and R. Grosu, “A Mixed-Criticality Integration in Cyber-Physical Systems: A Heterogeneous Time-Triggered Architecture on a Hybrid SoC Platform,” in Computer Systems and Software Engineering: Concepts, Methodologies, Tools, and Applications: IGI Global, 2018, pp. 1153–1178.
[36] B. Sorkhpour and R. Obermaisser, “MeSViz: Visualizing Scenario-based Meta-Schedules for Adaptive Time-Triggered Systems,” in AmE 2018-Automotive meets Electronics; 9th GMM-Symposium, 2018, pp. 1–6.
[37] B. Hu, “Schedulability Analysis of General Task Model and Demand Aware Scheduling in Mixed-Criticality Systems,” Technische Universität München.
[38] H. Ahmadian, F. Nekouei, and R. Obermaisser, “Fault recovery and adaptation in time-triggered Networks-on-Chips for mixed-criticality systems,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, (ReCoSoC 2017): July 12-14, 2017, Madrid, Spain : proceedings, Madrid, Spain, 2017, pp. 1–8.
[39] R. Trüb, G. Giannopoulou, A. Tretter, and L. Thiele, “Implementation of partitioned mixed-criticality scheduling on a multi-core platform,” ACM Transactions on Embedded Computing Systems (TECS), vol. 16, no. 5s, p. 122, 2017.
[40] C. Schöler, “Novel scheduling strategies for future NoC and MPSoC architectures,” 2017.
[41] M. I. Huse, “FlexRay Analysis, Configuration Parameter Estimation, and Adversaries,” NTNU.
[42] W. Steiner, “Synthesis of Static Communication Schedules for Mixed-Criticality Systems,” in 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing workshops (ISORCW): 28-31 March 2011, Newport Beach, California, USA ; proceedings, Newport Beach, CA, USA, 2011, pp. 11–18.
[43] G. Marchetto, S. Tahir, and M. Grosso, “A blocking probability study for the aethereal network-on-chip,” in Proceedings of 2016 11th International Design & Test Symposium (IDT): December 18-20-2016, Hammamet, Tunisia, Hammamet, Tunisia, 2016, pp. 104–109.
[44] M. Ruff, “Evolution of local interconnect network (LIN) solutions,” in VTC2003-Fall Orlando: 2003 IEEE 58th Vehicular Technology Conference : proceedings : 6-9 October, 2003, Orlando, Florida, USA, Orlando, FL, USA, 2004, 3382-3389 Vol.5.
[45] R. B. Atitallah, S. Niar, A. Greiner, S. Meftali, and J. L. Dekeyser, “Estimating Energy Consumption for an MPSoC Architectural Exploration,” in Lecture Notes in Computer Science, Architecture of Computing Systems – ARCS 2006, W. Grass, B. Sick, and K. Waldschmidt, Eds., Berlin, Heidelberg: Springer Berlin Heidelberg, 2006, pp. 298–310.
[46] U. U. Tariq, H. Wu, and S. Abd Ishak, “Energy-Aware Scheduling of Conditional Task Graphs on NoC-Based MPSoCs,” in Proceedings of the 51st Hawaii International Conference on System Sciences, 2018.
[47] Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain: ACM Press.
[48] A. B. Mehta, “Clock Domain Crossing (CDC) Verification,” in ASIC/SoC Functional Design Verification.

[49] Mecanismo de controle de QoS através de DFS em MPSOCS: Pontifícia Universidade Católica do Rio Grande do Sul; Porto Alegre, 2014.
[50] Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, and Lionel Havet, “Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor,”
[51] B. D. de Dinechin and A. Graillat, “Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor,” in Proceedings of the 10th International Workshop on Network on Chip Architectures – NoCArc’17, Cambridge, MA, USA, 2017, pp. 1–6.
[52] KALRAY Corporation, Kalray’s MPPA network-on-chip. [Online] Available: http://www.kalrayinc.com/portfolio/processors/.
[53] I. Lee, J. Y. T. Leung, and S. H. Son, Handbook of real-time and embedded systems: CRC Press, 2007.
[54] Wikipedia, XtratuM – Wikipedia. [Online] Available: https://en.wikipedia.org/w/index.php?oldid=877711274. Accessed on: Feb. 11 2019.
[55] I. Ripoll et al., “Configuration and Scheduling tools for TSP systems based on XtratuM,” Data Systems In Aerospace (DASIA 2010), 2010.
[56] V. Brocal et al., “Xoncrete: a scheduling tool for partitioned real-time systems,” Embedded Real-Time Software and Systems, 2010.
[57] R. Jejurikar and R. Gupta, “Dynamic slack reclamation with procrastination scheduling in real-time embedded systems,” in Proceedings of the 42nd annual Design Automation Conference, 2005, pp. 111–116.
[58] H. Li, S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy, “Deterministic clock gating for microprocessor power reduction,” in The 9th international symposium on high-performance computer architecture, Anaheim, CA, USA, 2003, pp. 113–122.
[59] H. Matsutani, M. Koibuchi, H. Nakamura, and H. Amano, “Run-Time Power-Gating Techniques for Low-Power On-Chip Networks,” in Low Power Networks-on-Chip.
[60] P. W. Cook et al., “Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors,” IEEE Micro, vol. 20, no. 6, pp. 26–44, 2000.
[61] W. Kim, J. Kim, and S. L. Min, “Dynamic voltage scaling algorithm for dynamic-priority hard real-time systems using slack time analysis,” in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 788–794.
[62] D. M. Brooks et al., “Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors,” IEEE Micro, vol. 20, no. 6, pp. 26–44, 2000.
[63] S. Prabhu, Ocin_tsim – A DVFS Aware Simulator for NoC Design Space Exploration and Optimization. [College Station, Tex.]: [Texas A & M University], 2010.
[64] A. Bianco, P. Giaccone, and N. Li, “Exploiting Dynamic Voltage and Frequency Scaling in networks on chip,” in IEEE 13th International Conference on High Performance Switching and Routing (HPSR), 2012, Belgrade, Serbia, 2012, pp. 229–234.
[65] M. Caria, F. Carpio, A. Jukan, and M. Hoffmann, “Migration to energy efficient routers: Where to start?,” in IEEE International Conference on Communications (ICC), 2014: 10-14 June 2014, Sydney, Australia, Sydney, NSW, 2014, pp. 4300–4306.
[66] D. M. Brooks et al., “Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors,” IEEE Micro, vol. 20, no. 6, pp. 26–44, 2000.
[67] S. Chai, Y. Li, J. Wang, and C. Wu, “An energy-efficient scheduling algorithm for computation-intensive tasks on NoC-based MPSoCs,” Journal of Computational Information Systems, vol. 9, no. 5, pp. 1817–1826, 2013.
[68] P. K. Sharma, S. Biswas, and P. Mitra, “Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip,” Microprocessors and Microsystems, vol. 64, pp. 88–100, 2019.
[69] H. M. Kamali, K. Z. Azar, and S. Hessabi, “DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture,” IEEE Trans. Comput., vol. 67, no. 2, pp. 208–221, 2018.
[70] H. Farrokhbakht, H. M. Kamali, and S. Hessabi, “SMART,” in Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip – NOCS ’17, Seoul, Republic of Korea, 2017, pp. 1–8.
[71] W. Hu, X. Tang, B. Xie, T. Chen, and D. Wang, “An Efficient Power-Aware Optimization for Task Scheduling on NoC-based Many-core System,” in 2010 10th IEEE International Conference on Computer and Information Technology, Bradford, United Kingdom, 2010, pp. 171–178.

[72] H. F. Sheikh and I. Ahmad, “Simultaneous optimization of performance, energy and temperature for DAG scheduling in multi-core processors,” in Green Computing Conference (IGCC), 2012 International, 2012, pp. 1–6.
[73] J. Hu and R. Marculescu, “Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints,” in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, pp. 234–239.
[74] H. Bokhari, H. Javaid, M. Shafique, J. Henkel, and S. Parameswaran, “darkNoC,” in Proceedings of the 51st Annual Design Automation Conference, San Francisco, CA, USA, 2014, pp. 1–6.
[75] H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, “Dynamic and aggressive scheduling techniques for power-aware real-time systems,” in 22nd IEEE real-time systems symposium: (RTSS 2001), London, UK, 2001, pp. 95–105.
[76] R. Jejurikar and R. Gupta, “Dynamic slack reclamation with procrastination scheduling in real-time embedded systems,” in DAC 42, San Diego, California, USA, 2005, p. 111.
[77] G. Ma, L. Gu, and N. Li, “Scenario-Based Proactive Robust Optimization for Critical-Chain Project Scheduling,” J. Constr. Eng. Manage., vol. 141, no. 10, p. 4015030, 2015.
[78] H. K. Mondal and S. Deb, “Power-and performance-aware on-chip interconnection architectures for many-core systems,” IIIT-Delhi.
[79] J. Wang et al., “Designing Voltage-Frequency Island Aware Power-Efficient NoC through Slack Optimization,” in International Conference on Information Science and Applications (ICISA), 2014: 6-9 May 2014, Seoul, South Korea, Seoul, South Korea, 2014, pp. 1–4.
[80] K. Han, J.-J. Lee, J. Lee, W. Lee, and M. Pedram, “TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 37, no. 2, pp. 458–471, 2018.
[81] D. Li and J. Wu, “Energy-efficient contention-aware application mapping and scheduling on NoC-based MPSoCs,” Journal of Parallel and Distributed Computing, vol. 96, pp. 1–11, 2016.
[82] W. Y. Lee, Y. W. Ko, H. Lee, and H. Kim, “Energy-efficient scheduling of a real-time task on dvfs-enabled multi-cores,” in Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009, pp. 273–277.
[83] B. Sprunt, L. Sha, and J. Lehoczky, “Aperiodic task scheduling for Hard-Real-Time systems,” Real-Time Syst, vol. 1, no. 1, pp. 27–60, 1989.
[84] J. K. Strosnider, J. P. Lehoczky, and L. Sha, “The deferrable server algorithm for enhanced aperiodic responsiveness in hard real-time environments,” IEEE Trans. Comput., vol. 44, no. 1, pp. 73–91, 1995.
[85] N. Chatterjee, S. Paul, and S. Chattopadhyay, “Task mapping and scheduling for network-on-chip based multi-core platform with transient faults,” Journal of Systems Architecture, vol. 83, pp. 34–56, 2018.
[86] R. N. Mahapatra and W. Zhao, “An energy-efficient slack distribution technique for multimode distributed real-time embedded systems,” IEEE Trans. Parallel Distrib. Syst., vol. 16, no. 7, pp. 650–662, 2005.
[87] G. Avni, S. Guha, and G. Rodriguez-Navas, “Synthesizing time-triggered schedules for switched networks with faulty links,” in Proceedings of the 13th International Conference on Embedded Software, Pittsburgh, Pennsylvania, 2016, pp. 1–10.
[88] F. Benhamou, Principle and Practice of Constraint Programming – CP 2006: 12th International Conference, CP 2006, Nantes, France, September 25-29, 2006, Proceedings. Berlin Heidelberg: Springer-Verlag, 2006.
[89] Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems, 2011.
[90] A. Murshed, R. Obermaisser, H. Ahmadian, and A. Khalifeh, “Scheduling and allocation of time-triggered and event-triggered services for multi-core processors with networks-on-a-chip,” pp. 1424–1431.
[91] F. Wang, C. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, “Variation-aware task allocation and scheduling for MPSoC,” in IEEE/ACM International Conference on Computer-Aided Design, 2007, San Jose, CA, USA, 2007, pp. 598–603.
[92] D. Mirzoyan, B. Akesson, and K. Goossens, “Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs,” ACM Trans. Embed. Comput. Syst., vol. 13, no. 2s, pp. 1–24, 2014.
[93] C. MacLean and G. COWIE, Data flow graph: Google Patents.
[94] S. K. Baruah, A. Burns, and R. I. Davis, “Response-Time Analysis for Mixed Criticality Systems,” in IEEE 32nd Real-Time Systems Symposium (RTSS), 2011, Vienna, Austria, 2011, pp. 34–43.
[95] A. Burns and S. Baruah, “Timing Faults and Mixed Criticality Systems,” in Lecture notes in computer science, 0302-9743, 6875. Festschrift, Dependable and historic computing: Essays dedicated to Brian Randell on the occasion of his 75th birthday/ Cliff B. Jones, John L. Lloyd (eds.), B. Randell, C. B. Jones, and J. L. Lloyd, Eds., Heidelberg: Springer, 2011, pp. 147–166.
[96] P. Ekberg and W. Yi, “Outstanding Paper Award: Bounding and Shaping the Demand of Mixed-Criticality Sporadic Tasks,” in Proceedings of The 24th Euromicro Conference on Real-Time Systems: 10-13 July 2012, Pisa, Italy, Pisa, Italy, 2012, pp. 135–144.
[97] M. R. Garey, D. S. Johnson, and L. Stockmeyer, “Some simplified NP-complete problems,” in Proceedings of the sixth annual ACM symposium on Theory of computing – STOC ’74, Seattle, Washington, United States, 1974, pp. 47–63.
[98] L. Su et al., “Synthesizing Fault-Tolerant Schedule for Time-Triggered Network Without Hot Backup,” IEEE Trans. Ind. Electron., vol. 66, no. 2, pp. 1345–1355, 2019.
[99] A. Carvalho Junior, M. Bruschi, C. Santana, and J. Santana, “Green Cloud Meta-Scheduling : A Flexible and Automatic Approach,” (eng), Journal of Grid Computing : From Grids to Cloud Federations, vol. 14, no. 1, pp. 109–126, http://dx.doi.org/10.1007/s10723-015-9333-z, 2016.
[100] T. Tiendrebeogo, “Prospect of Reduction of the GreenHouse Gas Emission by ICT in Africa,” in e-Infrastructure and e-Services.
[101] Deutsche Welle (www.dw.com), Carmaker BMW to invest heavily in battery cell center | DW | 24.11.2017. [Online] Available: https://p.dw.com/p/2oD3x. Accessed on: Dec. 03 2018.
[102] G. Fohler, “Changing operational modes in the context of pre run-time scheduling,” IEICE transactions on information and systems, vol. 76, no. 11, pp. 1333–1340, 1993.
[103] H. Jung, H. Oh, and S. Ha, “Multiprocessor scheduling of a multi-mode dataflow graph considering mode transition delay,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, no. 2, p. 37, 2017.
[104] A. Das, A. Kumar, and B. Veeravalli, “Energy-Aware Communication and Remapping of Tasks for Reliable Multimedia Multiprocessor Systems,” in IEEE 18th International Conference on Parallel and Distributed Systems (ICPADS), 2012, Singapore, Singapore, 2012, pp. 564–571.
[105] S. A. Ishak, H. Wu, and U. U. Tariq, “Energy-Aware Task Scheduling on Heterogeneous NoC-Based MPSoCs,” in IEEE 35th IEEE International Conference on Computer Design: ICCD 2017 : 5-8 November 2017 Boston, MA, USA : proceedings, Boston, MA, 2017, pp. 165–168.

[106] C. A. Floudas and V. Visweswaran, “Quadratic Optimization,” in Nonconvex Optimization and Its Applications, vol. 2, Handbook of Global Optimization, R. Horst and P. M. Pardalos, Eds., Boston, MA, s.l.: Springer US, 1995, pp. 217–269.
[107] R. Lazimy, “Mixed-integer quadratic programming,” Mathematical Programming, vol. 22, no. 1, pp. 332–349, 1982.
[108] A. Majd, G. Sahebi, M. Daneshtalab, and E. Troubitsyna, “Optimizing scheduling for heterogeneous computing systems using combinatorial meta-heuristic solution,” in 2017 IEEE SmartWorld: Ubiquitous Intelligence & Computing, Advanced & Trusted Computed, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI) : 2017 conference proceedings : San Francisco Bay Area, California, USA, August 4-8, 2017, San Francisco, CA, 2017, pp. 1–8.
[109] B. Xing and W.-J. Gao, “Imperialist Competitive Algorithm,” in Intelligent Systems Reference Library, Innovative computational intelligence: A rough guide to 134 clever algorithms, B. Xing and W.-J. Gao, Eds., New York NY: Springer Berlin Heidelberg, 2013, pp. 203–209.
[110] J. D. Foster, A. M. Berry, N. Boland, and H. Waterer, “Comparison of Mixed-Integer Programming and Genetic Algorithm Methods for Distributed Generation Planning,” IEEE Trans. Power Syst., vol. 29, no. 2, pp. 833–843, 2014.
[111] J. Yin, P. Zhou, A. Holey, S. S. Sapatnekar, and A. Zhai, “Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems,” in ISPLED’12: Proceedings of the international symposium on low power electronics and design, Redondo Beach, California, USA, 2012, p. 57.
[112] J. Falk et al., “Quasi-static scheduling of data flow graphs in the presence of limited channel capacities,” in The 13th IEEE Symposium on Embedded Systems for Real-time Multimedia: October 8-9, 2015, Amsterdam, Netherlands, Amsterdam, Netherlands, 2015, pp. 1–10.
[113] T. Wei, P. Mishra, K. Wu, and J. Zhou, “Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems,” Journal of Systems and Software, vol. 85, no. 6, pp. 1386–1399, 2012.
[114] M. J. Ryan, “A Case Study on the Impact of Convergence on Physical Architectures—The Tactical Communications System,”
[115] Y. Huang and D. P. Palomar, “Randomized Algorithms for Optimal Solutions of Double-Sided QCQP With Applications in Signal Processing,” IEEE Trans. Signal Process., vol. 62, no. 5, pp. 1093–1108, 2014.

[116] X. Cai, W. Hu, T. Ma, and R. Ma, “A hybrid scheduling algorithm for reconfigurable processor architecture,” in Proceedings of the 13th IEEE Conference on Industrial Electronics and Applications (ICIEA 2018): 31 May-2 June 2018 Wuhan, China, Wuhan, 2018, pp. 745–749.
[117] P.-A. Hsiung and J.-S. Shen, Dynamic reconfigurable network-on-chip design: Innovations for computational processing and communication. Hershey, Pa.: IGI Global, 2010.
[118] R. Misener and C. A. Floudas, “Global optimization of mixed-integer quadratically-constrained quadratic programs (MIQCQP) through piecewise-linear and edge-concave relaxations,” Mathematical Programming, vol. 136, no. 1, pp. 155–182, 2012.
[119] D. Axehill, “Applications of integer quadratic programming in control and communication,” Institutionen för systemteknik.
[120] A. Nemirovskii, “Several NP-hard problems arising in robust stability analysis,” Math. Control Signal Systems, vol. 6, no. 2, pp. 99–105, 1993.
[121] A. Sarwar, “Cmos power consumption and cpd calculation,” Proceeding: Design Considerations for Logic Products, 1997.
[122] S. Kaxiras and M. Martonosi, “Computer Architecture Techniques for Power-Efficiency,” Synthesis Lectures on Computer Architecture, vol. 3, no. 1, pp. 1–207, 2008.
[123] D. Kouzoupis, G. Frison, A. Zanelli, and M. Diehl, “Recent Advances in Quadratic Programming Algorithms for Nonlinear Model Predictive Control,” Vietnam Journal of Mathematics, vol. 46, no. 4, pp. 863–882, 2018.
[124] R. Fourer, “Strategies for “Not Linear” Optimization,” Houston, TX, Mar. 6 2014.
[125] L. A. Cortes, P. Eles, and Z. Peng, “Quasi-Static Scheduling for Multiprocessor Real-Time Systems with Hard and Soft Tasks,” in 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications: 17-19 August 2005, Hong Kong, China : proceedings, Hong Kong, China, 2005, pp. 422–428.
[126] L. Benini, “Platform and MPSoC Design,”
[127] R. Obermaisser and P. Peti, “A Fault Hypothesis for Integrated Architectures,” in Proceedings of the Fourth Workshop on Intelligent Solutions in Embedded Systems: Vienna University of Technology, Vienna, Austria, 2006 June 30, Vienna, Austria, 2005, pp. 1–18.

[128] R. Obermaisser et al., “Adaptive Time-Triggered Multi-Core Architecture,” Designs, vol. 3, no. 1, p. 7, https://www.mdpi.com/2411-9660/3/1/7/pdf, 2019.
[129] IBM, IBM ILOG CPLEX Optimization Studio CPLEX User’s Manual: IBM, 1987-2016.
[130] Chart Component and Control Library for .NET (C#/VB), Java, C++, ASP, COM, PHP, Perl, Python, Ruby, ColdFusion. [Online] Available: https://www.advsofteng.com/product.html. Accessed on: Jan. 10 2019.
[131] J. Ellson, E. Gansner, L. Koutsofios, S. C. North, and G. Woodhull, “Graphviz—open source graph drawing tools,” in International Symposium on Graph Drawing, 2001, pp. 483–484.
[132] T. Lei and S. Kumar, “Algorithms and tools for network on chip based system design,” in Chip in sampa, Sao Paulo, Brazil, 2003, pp. 163–168.
[133] G. D. Micheli and L. Benini, “Powering networks on chips: energy-efficient and reliable interconnect design for SoCs,” in isss, 2001, pp. 33–38.